Static random access memories (SRAMs) have less storage capacity but higher operating speed than dynamic random access memories (DRAMs). Therefore, SRAMs have been widely used in cache memories of computers and various portable electronic appliances that require high operating speeds.
SRAM cells may be classified into thin film transistor (TFT) cells and full complementary metal-oxide semiconductor (FCMOS) cells. A FCMOS cell includes a plurality of pull-up transistors and a plurality of pull-down transistors that constitute a latch, as well as a plurality of transistors that access the latch.
As the integration density of semiconductor memory devices increases, the size of the memory cells in the device decrease, which results in a decrease in the size of the metal contacts. However, as the size of metal contacts decreases, it becomes more difficult to accurately pattern metal contacts, and, thus, the frequency of defects in the fabrication of metal contacts increases. In particular, a pair of adjacent contacts in an SRAM cell may be electrically connected or bridged. As is known to those of skill in the art, certain contacts in a highly integrated SRAM device may have a longitudinal axis and a latitudinal axis, and may be disposed close to one another along the direction of the longitudinal axis. Thus, these adjacent contacts may be unintentionally electrically connected during fabrication of the SRAM device.
As a result, it may be useful to test an SRAM device to determine whether there is a bridge between contacts in SRAM cells. An SRAM device may be tested using defect inspection tools which mostly are optical equipment. However, it may take a considerable amount of time to test an SRAM device, and, thus, productivity may be reduced.